1. Field of the Invention
The present invention relates to a large-scale-integration circuit apparatus (LSI) for an image and/or graphics processing system, and more particularly to a peripheral LSI for image memories suitable for using standard-type random access memories which are broadly used.
2. Description of the Related Art
Image and/or graphics processing systems mostly use dynamic type random access memories (DRAM) which have made a remarkable progress in higher integration density to satisfy the demand for image memories having a greater capacity. The following are main requirements for the image memory;
(1) to be capable of reading out data for display on an image monitor, and PA0 (2) to allow an image and/or graphics processer access (read/write). PA0 (1) a nibble or page mode access, whereby DRAM is capable of operating at a high speed; PA0 (2) a real time data processing, in which a processing of data read out from the image memory, such as a density conversion of pixel data, a calculation between images, a convolution and the like, is executed at the same speed as the display and a processed data is written into the image memory at the same speed again, and/or in which an image data taken by a television camera is written into the image memory at the high speed (the former is especially called a feedback processing, hereinafter); PA0 (3) a modification-write operation, in which a modification processing, such as logical and/or arithmetic operation, is carried out between an image data existing in the image memory and an image data to the written afresh and a modified data is written into the image memory again; PA0 (4) a block-write operation for high speed processing, in which an image data of plural pixels is written into the image memory in parallel; PA0 (5) an arbitrary region processing, in which the data of pixels can be processed pixel by pixel without depending upon the delimitation in the parallel read/write operation of the memories in a case of the feedback processing or the movement of the image (scroll); and PA0 (6) a smooth scroll processing in a transverse direction in image display.
Usually, a memory cycle time of a DRAM is about 300 nano-seconds. When a DRAM is used for the image memory, the operational speed of the image memory becomes around 3 megapixels per second. On the other hand, the display speed in the image monitor is 6 to 100 megapixels per second. Therefore, a plurality of DRAMs in which data for pixels are stored are operated in parallel in order to cope with the difference in the operational speed. For the purpose of this parallel operation of plural DRAMs, a large number of peripheral circuits have been necessary according to conventional practice.
As an LSI for this image memory peripheral circuit, a graphics LSI which can designate one of a plurality of pixels being processed in parallel and can read out the image data of the pixel 64 an external processer or write it into the image memory, is described in the article entitled "Color-graphics controller chip set reduces parts count, incorporates microcomputer" in Electronics/Apr. 19 (1984), p.p. 166-168.
However, the known image memory peripheral LSI does not include the following functions: